FPGA Test and Coverage

Authors:
Shahin Toutounchi;Andrew Lai
Affiliations:
-;-
Venue:
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Year:
2002

Citing 0
Cited 4

Minimizing the number of test configurations for FPGAs

Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
System-on-Chip Test Architectures: Nanometer Design for Testability

System-on-Chip Test Architectures: Nanometer Design for Testability
Test compression for dynamically reconfigurable processors

ACM Transactions on Reconfigurable Technology and Systems (TRETS)
A novel full coverage test method for CLBs in FPGA (abstract only)

Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays

Quantified Score

Hi-index	0.00

Visualization

Abstract

This paper presents FPGA test and coverage methodology. BIST and "shift register" styles oftest is discussed. Gate level fault grading results are then presented. Use of "iterative logic unit" and its impact on test and fault grading is discussed