Introduction to data compression
Introduction to data compression
Configuration Compression for the Xilinx XC6200 FPGA
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Architecture Exploration for a Reconfigurable Architecture Template
IEEE Design & Test
Configuration Compression for Virtex FPGAs
FCCM '01 Proceedings of the the 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Configuration bitstream compression for dynamically reconfigurable FPGAs
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
A new approach to compress the configuration information of programmable devices
Proceedings of the conference on Design, automation and test in Europe: Designers' forum
Partial Reconfiguration Bitstream Compression for Virtex FPGAs
CISP '08 Proceedings of the 2008 Congress on Image and Signal Processing, Vol. 5 - Volume 05
Hardware Decompression Techniques for FPGA-Based Embedded Systems
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Configuration compression for FPGA-based embedded systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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We present the world's first test compression technique that features automation of compression rules for test time reduction on dynamically reconfigurable processors. Evaluations on an actual 40-nm product show that our technique achieves a 2.7 times compression ratio for original configuration information (better than does GZIP), the peak decompression bandwidth of 1.6 GB/s, and 2.7 times shorter test times.