Ultra-Fast Downloading of Partial Bitstreams through Ethernet
ARCS '09 Proceedings of the 22nd International Conference on Architecture of Computing Systems
Test compression for dynamically reconfigurable processors
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
A dynamically reconfigurable communication architecture for multicore embedded systems
Journal of Systems Architecture: the EUROMICRO Journal
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An adaptive LZW algorithm for compressing partial bitstreams of Virtex FPGAs was presented. The adaptations of algorithm were based on analysis of the three-level data regularity of the configuration bitstreams. Partial bitstreams were created through Xilinx module-based partial reconfiguration flow. The experiment demonstrated down to 43.69% compression ratio for partial bitstreams of several real-world applications.