Field-programmable gate arrays
Field-programmable gate arrays
Diagnosing programmable interconnect systems for FPGAs
Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays
Evaluation of FPGA resources for built-in self-test of programmable logic blocks
Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays
RAM-based FPGA's: a test approach for the configurable logic
Proceedings of the conference on Design, automation and test in Europe
Field-Programmable Gate Array Technology
Field-Programmable Gate Array Technology
Universal Fault Diagnosis for Lookup Table FPGAs
IEEE Design & Test
Testing the Interconnect of RAM-Based FPGAs
IEEE Design & Test
Testing of programmable logic devices (PLD) with faulty resources
DFT '97 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems
SRAM-Based FPGAs: A Fault Model for the Configurable Logig Modules
FPL '98 Proceedings of the 8th International Workshop on Field-Programmable Logic and Applications, From FPGAs to Computing Paradigm
SRAM-based FPGA's: testing the LUT/RAM modules
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Universal test complexity of field-programmable gate arrays
ATS '95 Proceedings of the 4th Asian Test Symposium
A Test Methodology for Interconnect Structures of LUT-based FPGAs
ATS '96 Proceedings of the 5th Asian Test Symposium
Test Pattern and Test Configuration Generation Methodology for the Logic of RAM-Based FPGA
ATS '97 Proceedings of the 6th Asian Test Symposium
Testing for the programming circuit of LUT-based FPGAs
ATS '97 Proceedings of the 6th Asian Test Symposium
SRAM-Based FPGA's: Testing the Interconnect/Logic Interface
ATS '98 Proceedings of the 7th Asian Test Symposium
Testing memory modules in SRAM-based configurable FPGAs
MTDT '97 Proceedings of the 1997 IEEE International Workshop on Memory Technology, Design and Testing
An approach for testing programmable/configurable field programmable gate arrays
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Test of RAM-based FPGA: methodology and application to the interconnect
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
Test, diagnosis and fault simulation of embedded RAM modules in SRAM-based FPGAs
Microelectronic Engineering
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This paper describes an approach to minimize thenumber of test configurations for testing the logic cells of aRAM-based FPGA taking into account the configurability of suchflexible device. The proposed approach concerns the XILINX 4000 family. On this example of FPGA, a bottom-up test technique is firstused to generate test configurations for the elementary modules, thentest configurations for a single logic cell, and finally testconfigurations for the m × m array of logic cells. In thisbottom-up technique, it is shown that the key point is theminimization of the number of test configurations for a logic cell.An approach for the logic cell of the XILINX4000 family is thendescribed to define a minimum number of test configurations knowingthe test configurations of its logic modules. This approach givesonly 5 test configurations for the XILINX4000 family while theprevious published works concerning Boolean testing of this FPGAfamily gives 8 or 21 test configurations.