Methodologies for Tolerating Cell and Interconnect Faults in FPGAs
IEEE Transactions on Computers
RAM-based FPGA's: a test approach for the configurable logic
Proceedings of the conference on Design, automation and test in Europe
Novel technique for testing FPGAs
Proceedings of the conference on Design, automation and test in Europe
Universal Fault Diagnosis for Lookup Table FPGAs
IEEE Design & Test
Testing the Interconnect of RAM-Based FPGAs
IEEE Design & Test
Test of RAM-based FPGA: methodology and application to the interconnect
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
NOVEL TECHNIQUE FOR BUILT-IN SELF-TEST OF FPGA INTERCONNECTS
ITC '00 Proceedings of the 2000 IEEE International Test Conference
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Detecting, diagnosing, and tolerating faults in SRAM-based field programmable gate arrays: a survey
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
Testing Layered Interconnection Networks
IEEE Transactions on Computers
Application-Specific Bridging Fault Testing of FPGAs
Journal of Electronic Testing: Theory and Applications
A novel FPGA local interconnect test scheme and automatic TC derivation/generation
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Desing and test of systems on a chip
Defect tolerance at the end of the roadmap
Nano, quantum and molecular computing
Fault tolerance of switch blocks and switch block arrays in FPGA
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Application-dependent testing of FPGAs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Fine grain faults diagnosis of FPGA interconnect
Microprocessors & Microsystems
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This paper considers the diagnosis of field programmable interconnect systems (FPIS) in which programmable grids made of switches are included. For this type of interconnects, the number of times the grid must be programmed and the programming sequence of the switches an two of the most important figures of merit for full diagnosis (defection and location with no aliasing and confounding). A hierarchical approach to diagnosis is proposed and fully characterized. The application of this technique to commercially available FPIS such as FPGAs, is discussed. It is shown that the proposed diagnostic technique can be applied to the general purpose interconnect of the FPGAs in the 3000 family by Xilinx.