Diagnosing programmable interconnect systems for FPGAs
Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays
Adaptive Fault Detection and Diagnosis of RAM Interconnects
Journal of Electronic Testing: Theory and Applications
Testing the Interconnect of RAM-Based FPGAs
IEEE Design & Test
Built-in self-test of FPGA interconnect
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A Test Methodology for Interconnect Structures of LUT-based FPGAs
ATS '96 Proceedings of the 5th Asian Test Symposium
A Diagnosis Method for Interconnects in SRAM Based FPGAs
ATS '98 Proceedings of the 7th Asian Test Symposium
On the diagnosis of programmable interconnect systems: Theory and application
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Enhanced Bist-Based Diagnosis of FPGAs via Boundary Scan Access
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Diagnosis of interconnects and FPICs using a structured walking-1 approach
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
FPGA test time reduction through a novel interconnect testing scheme
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Reconfigurable systems
Application-Specific Bridging Fault Testing of FPGAs
Journal of Electronic Testing: Theory and Applications
A novel FPGA local interconnect test scheme and automatic TC derivation/generation
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Desing and test of systems on a chip
Efficient on-line interconnect testing in FPGAs with provable detectability for multiple faults
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Fault tolerance of switch blocks and switch block arrays in FPGA
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An Automated BIST Architecture for Testing and Diagnosing FPGA Interconnect Faults
Journal of Electronic Testing: Theory and Applications
Application-dependent testing of FPGAs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
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This paper presents the first BIST approach for testinginterconnects of SRAM-based FPGAs using error controlcoding. The proposed scheme requires a total of six testconfigurations and has superior multiple fault coverageon wire segment stuck-at, stuck-open and bridging faults,programmable switch stuck on/off faults, and thecombinations of these faults in global routing resources.