A novel FPGA local interconnect test scheme and automatic TC derivation/generation

Authors:
Xiaoling Sun;K. Ogden;H. Chan;P. Trouborst
Affiliations:
Department of Electrical and Computer Engineering, University of Alberta, Second Floor, ECERF Bldg., Edmonton, AB, Canada T6G 2V4;Department of Electrical and Computer Engineering, University of Alberta, Second Floor, ECERF Bldg., Edmonton, AB, Canada T6G 2V4;Department of Electrical and Computer Engineering, University of Alberta, Second Floor, ECERF Bldg., Edmonton, AB, Canada T6G 2V4;LogicVision (Canada) Inc. and Hardware Design Solutions, Nortel Networks, Ottawa, ON, Canada K2C 3V5
Venue:
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Desing and test of systems on a chip
Year:
2004

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Abstract

This paper presents a novel local interconnect testing scheme for field programmable gate arrays (FPGAs). To maximize parallel testing, error-detecting code is used for testing one portion of interconnects and functional test of D latch for another in a test configuration (TC). A polynomial run time algorithm is introduced for deriving a minimal set of TCs. An in-house CAD tool is developed to automate the generation of device configurations from the set of TCs.