Testing configurable LUT-based FPGA's
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On-line fault detection for bus-based field programmable gate arrays
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Universal Fault Diagnosis for Lookup Table FPGAs
IEEE Design & Test
BIST-Based Diagnostics of FPGA Logic Blocks
Proceedings of the IEEE International Test Conference
On the Necessity of On-line-BIST in Safety-Critical Applications - A Case-Study
FTCS '99 Proceedings of the Twenty-Ninth Annual International Symposium on Fault-Tolerant Computing
An approach for testing programmable/configurable field programmable gate arrays
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Built-in self-test of logic blocks in FPGAs (Finally, a free lunch: BIST without overhead!)
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Enhanced Bist-Based Diagnosis of FPGAs via Boundary Scan Access
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
NOVEL TECHNIQUE FOR BUILT-IN SELF-TEST OF FPGA INTERCONNECTS
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Improving On-Line BIST-Based Diagnosis for Roving STARs
IOLTW '00 Proceedings of the 6th IEEE International On-Line Testing Workshop (IOLTW)
On-Line BIST and Diagnosis of FPGA Interconnect Using Roving STARs
IOLTW '01 Proceedings of the Seventh International On-Line Testing Workshop
Using Roving STARs for On-Line Testing and Diagnosis of FPGAs in Fault-Tolerant Applications
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Efficient on-line testing of FPGAs with provable diagnosabilities
Proceedings of the 41st annual Design Automation Conference
High-diagnosability online built-in self-test of FPGAs via iterative bootstrapping
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
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We present a very effective on-line interconnect built-in-self-test (BIST) method I-BIST for FPGAs that uses a combination of the following novel techniques: a track-adjacent and a switch-adjacent (also called "mirror adjacent") pairwise net comparison mechanism that achieves high detectability, a carefully designed set of only five net-configurations that cover all types and locations of wire-segment and switch faults, a 2-phase global-detailed testing approach, and a divide-and-conquer technique used in detailed testing to quickly narrow down the set of potential suspect interconnects that are then detail-diagnosed. These techniques result in I-BIST having provable detectability in the presence of an unbounded number of multiple faults, very high diagnosability of 99-100% even for high fault densities of up to 10% that are expected in emerging nano-scale technologies, and much lower test times or fault latencies than the previous best interconnect BIST techniques. In particular, for application to on-line testing, our method re- quires 2n roving-tester (ROTE) configurations to test an entire n x n FPGA, while the previous best online interconnect BIST technique re- quires n2 configurations. Thus, I-BIST is an order of magnitude more time- as well as power-efficient, and will scale well with rapidly increas- ing FPGA device sizes that are expected in emerging technologies.