IEEE Transactions on Computers - Special issue on fault-tolerant computing
Methodologies for Tolerating Cell and Interconnect Faults in FPGAs
IEEE Transactions on Computers
Regular Sparse Crossbar Concentrators
IEEE Transactions on Computers
Generating highly-routable sparse crossbars for PLDs
FPGA '00 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays
Interconnect testing in cluster-based FPGA architectures
Proceedings of the 37th Annual Design Automation Conference
Handbook of Applied Cryptography
Handbook of Applied Cryptography
Architecture and CAD for Deep-Submicron FPGAs
Architecture and CAD for Deep-Submicron FPGAs
Diagnosis of interconnect faults in cluster-based FPGA architectures
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Testing the Interconnect of RAM-Based FPGAs
IEEE Design & Test
Built-in self-test of FPGA interconnect
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Current status and future trend on CAD tools for VLSI testing
ATS '00 Proceedings of the 9th Asian Test Symposium
A Test Methodology for Interconnect Structures of LUT-based FPGAs
ATS '96 Proceedings of the 5th Asian Test Symposium
Testing and Diagnosis of Interconnect Structures in FPGAs
ATS '98 Proceedings of the 7th Asian Test Symposium
Emerging Trends in VLSI Test and Diagnosis
WVLSI '00 Proceedings of the IEEE Computer Society Annual Workshop on VLSI (WVLSI'00)
NOVEL TECHNIQUE FOR BUILT-IN SELF-TEST OF FPGA INTERCONNECTS
ITC '00 Proceedings of the 2000 IEEE International Test Conference
An Automated BIST Architecture for Testing and Diagnosing FPGA Interconnect Faults
Journal of Electronic Testing: Theory and Applications
A cost-efficient self-configurable BIST technique for testing multiplexer-based FPGA interconnect
Journal of Electronic Testing: Theory and Applications
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As device densities increase, testing cost is becoming a larger portion of the overall FPGA manufacturing cost. We present an approach to speed up testing FPGA interconnect by reconfiguring it during the test. Simple additions are made to create feedback shift register structures, which considerably reduce the number of test configurations for the switching matrix interconnect. This new testing architecture reduces switching matrix test time by 66% and the diagnosis time by 72%. The additions are transparent to the users both in terms of speed and functionality.