Using simulated annealing to design good codes
IEEE Transactions on Information Theory
Introduction to algorithms
Plasma: an FPGA for million gate systems
Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays
Entropy, counting, and programmable interconnect
Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays
Regular Sparse Crossbar Concentrators
IEEE Transactions on Computers
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
Architecture and CAD for Deep-Submicron FPGAs
Architecture and CAD for Deep-Submicron FPGAs
Teramac-configurable custom computing
FCCM '95 Proceedings of the IEEE Symposium on FPGA's for Custom Computing Machines
Crosspoint complexity of sparse crossbar concentrators
IEEE Transactions on Information Theory
Using sparse crossbars within LUT
FPGA '01 Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays
FPGA test time reduction through a novel interconnect testing scheme
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
The SFRA: a corner-turn FPGA architecture
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
Testing Layered Interconnection Networks
IEEE Transactions on Computers
Proceedings of the 2014 ACM/SIGDA international symposium on Field-programmable gate arrays
Optimization of interconnects between accelerators and shared memories in dark silicon
Proceedings of the International Conference on Computer-Aided Design
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A method for evaluating and constructing sparse crossbars which are both area efficient and highly routable is presented. The evaluation method uses a network flow algorithm to accurately compute the percentage of random test vectors that can be routed. The construction method attempts to maximize the spread of the switch locations, such that any given subset of input wires can connect to as many output wires as possible. Based on Hall's Theorem, we argue that this increases the likelihood of routing.The hardest test vectors to route are those which attempt to use all of the crossbar outputs. Results in this paper show that area-efficient sparse crossbars can be constructed by providing more outputs than required and a sufficient number of switches. In a few specific case studies, it is shown that sparse crossbars with about 90% fewer switches than a full crossbar can be constructed, and these crossbars are capable of routing over 95% of randomly chosen routing vectors. In one case, a new switch matrix which can replace the one in the Altera FLEX8000 family is shown. This new switch matrix uses approximately 14% more transistors, yet can increase the routability of the most difficult test vectors from 1% to over 96%.