Entropy, counting, and programmable interconnect

Balancing interconnect and computation in a reconfigurable computing array (or, why you don't really want 100% LUT utilization)

FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays

Generating highly-routable sparse crossbars for PLDs

FPGA '00 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays

Rent's rule based switching requirements

Proceedings of the 2001 international workshop on System-level interconnect prediction

Post-placement interconnect entropy: how many configuration bits does a programmable logic device need?

Proceedings of the 2006 international workshop on System-level interconnect prediction

Designing efficient input interconnect blocks for LUT clusters using counting and entropy

Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays

Designing Efficient Input Interconnect Blocks for LUT Clusters Using Counting and Entropy

ACM Transactions on Reconfigurable Technology and Systems (TRETS) - Special edition on the 15th international symposium on FPGAs

Design Aspects of Multi-level Reconfigurable Architectures

Journal of Signal Processing Systems

Post-placement interconnect entropy

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation

Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation

Novel hardware processing unit for dynamic on-line entropy estimation of discrete time information

Digital Signal Processing