Entropy, counting, and programmable interconnect
Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
Compact, multilayer layout for butterfly fat-tree
Proceedings of the twelfth annual ACM symposium on Parallel algorithms and architectures
STOC '79 Proceedings of the eleventh annual ACM symposium on Theory of computing
Graph based analysis of 2-D FPGA routing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Design of minimum and uniform bipartites for optimum connection blocks of FPGA
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Design of FPGA interconnect for multilevel metalization
FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
Very Large Scale Spatial Computing
UMC '02 Proceedings of the Third International Conference on Unconventional Models of Computation
Guaranteeing the quality of services in networks on chip
Networks on chip
Design of FPGA interconnect for multilevel metallization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Unifying mesh- and tree-based programmable interconnect
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 2006 international workshop on System-level interconnect prediction
IBM Journal of Research and Development - POWER5 and packaging
Post-placement interconnect entropy
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On two-layer brain-inspired hierarchical topologies – a rent's rule approach –
Transactions on High-Performance Embedded Architectures and Compilers IV
Microprocessors & Microsystems
Location, location, location: the role of spatial locality in asymptotic energy minimization
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Exploration and optimization of a homogeneous tree-based application specific inflexible FPGA
Microelectronics Journal
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A Rent's Rule characterization of recursive bisection captures a measure of the locality in a netlist or graph. From this characterization, we know we can establish a lower bound on layout area implied by wiring. When applying this lower bound to the design of programmable or switched networks, we are ultimately concerned for both the switching requirements and the wiring requirements. Switch requirements are particularly important in conventional VLSI where (a) a switchpoint consumes considerably more area than a wire crossing and (b) switchpoints must reside on the active surface, whereas wiring may take place on any of several wire layers. The most straight-forward, limited-bisection switching networks have switching requirements which grow as $O(N^{2p})$, similar to wiring requirements. In practice, however, this leaves switching dominating wiring. We show that there are limited-bisection networks with $O(N)$ switching growth and highlight some of the tradeoffs between wire utilization and switching, routing complexity, routing guarantees, and switch latency within this design space.