Elements of information theory
Elements of information theory
Entropy, counting, and programmable interconnect
Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays
Extra-dimensional island-style FPGAs (abstract only)
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
Multi-terminal nets do change conventional wire length distribution models
Proceedings of the 2001 international workshop on System-level interconnect prediction
Rent's rule based switching requirements
Proceedings of the 2001 international workshop on System-level interconnect prediction
Architecture and CAD for Deep-Submicron FPGAs
Architecture and CAD for Deep-Submicron FPGAs
Design of FPGA interconnect for multilevel metalization
FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
Design of Interconnection Networks for Programmable Logic
Design of Interconnection Networks for Programmable Logic
FPGAs with Multidimensional Switch Topology
IEICE - Transactions on Information and Systems
Proceedings of the 2006 international workshop on System-level interconnect prediction
On a Pin Versus Block Relationship For Partitions of Logic Graphs
IEEE Transactions on Computers
Novel hardware processing unit for dynamic on-line entropy estimation of discrete time information
Digital Signal Processing
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We introduce the concept of post-placement interconnect entropy: the minimal number of bits required to describe a well-placed netlist, which has connection lengths distributed according to Rent's rule. The entropy is a function of the number N of cells in the netlist and the Rent exponent p. We derive an expression for the entropy per cell and show that it converges as N approaches infinity. The entropy provides an achievable lower bound on the number of configuration bits in a programmable logic device (PLD) [or field-programmable gate array (FPGA)] and a useful measure of its routing flexibility. Specific numerical values are computed for practical situations. For example, any scalable FPGA composed of 4-input lookup table cells would require 31 configuration bits per cell. We compare this to the actual number of configuration bits in a standard FPGA architecture. We generalize the bound to dimensions higher than two, and show that for any p there is an optimal dimension that minimizes the bound.