FPGAs with Multidimensional Switch Topology

Authors:
Yohei Matsumoto;Akira Masaki
Affiliations:
The author is with the Graduate School of Natural Science and Technology, Okayama University, Okayama-shi, 700-8530 Japan. E-mail: matumoto@giga.it.okayama-u.ac.jp,;The author is with the Faculty of Engineering, Okayama University, Okayama-shi, 700-8530 Japan
Venue:
IEICE - Transactions on Information and Systems
Year:
2005

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Abstract

This manuscript proposes an FPGA by embedding a multidimensional switch topology onto a two-dimensional chip. We show, using Rent's Rule, that this procedure reduces the number of switches. Then we propose the actual procedure and demonstrate that this does not increase metal wire density critically.