Reliable computer systems (2nd ed.): design and evaluation
Reliable computer systems (2nd ed.): design and evaluation
Reconfiguring Arrays with Faults Part I: Worst-Case Faults
SIAM Journal on Computing
Generic global placement and floorplanning
DAC '98 Proceedings of the 35th annual Design Automation Conference
Low overhead fault-tolerant FPGA systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A decade of reconfigurable computing: a visionary retrospective
Proceedings of the conference on Design, automation and test in Europe
NanoFabrics: spatial computing using molecular electronics
ISCA '01 Proceedings of the 28th annual international symposium on Computer architecture
Dragon2000: standard-cell placement tool for large industry circuits
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Hardware-assisted simulated annealing with application for fast FPGA placement
FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
Stochastic, spatial routing for hypergraphs, trees, and meshes
FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
PROUD: A Sea-Of-Gates Placement Algorithm
IEEE Design & Test
Universal Fault Diagnosis for Lookup Table FPGAs
IEEE Design & Test
A CMOS-Based Logic Cell for the Implementation of Self-Checking FPGAs
DFT '99 Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems
Defect and Fault Tolerance FPGAs by Shifting the Configuration Data
DFT '99 Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems
Compiling Application-Specific Hardware
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Molecular electronics: devices, systems and tools for gigagate, gigabit chips
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Quantum-dot cellular automata: computing by field polarization
Proceedings of the 40th annual Design Automation Conference
Minimizing the Number of Programming Steps for Diagnosis of Interconnect Faults in FPGAs
ATS '99 Proceedings of the 8th Asian Test Symposium
Practical Design of Globally-Asynchronous Locally-Synchronous Systems
ASYNC '00 Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems
A row-based FPGA for single and multiple stuck-at fault detection
DFT '95 Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
Defect tolerance on the Teramac custom computer
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
Tunable Fault Tolerance for Runtime Reconfigurable Architectures
FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
Dynamic Fault Tolerance in FPGAs via Partial Reconfiguration
FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
On the diagnosis of programmable interconnect systems: Theory and application
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Highly fault-tolerant parallel computation
FOCS '96 Proceedings of the 37th Annual Symposium on Foundations of Computer Science
Defects and Faults in Quantum Cellular Automata at Nano Scale
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
A Probabilistic-Based Design Methodology for Nanoscale Computation
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Spatial computation
Array-based architecture for FET-based, nanoscale electronics
IEEE Transactions on Nanotechnology
Hybrid CMOS/nanoelectronic digital circuits: devices, architectures, and design automation
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
The route to a defect tolerant LUT through artificial evolution
Genetic Programming and Evolvable Machines
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As feature sizes shrink closer to single digit nanometer dimensions, defect tolerance will become increasingly important. This is true whether the chips are manufactured using top-down methods, such as photolithography, or bottom-up assembly processes such as Chemically Assembled Electronic Nanotechnology (CAEN). In this chapter, we examine the consequences of this increased rate of defects, and describe a defect tolerance methodology centered around reconfigurable devices, a scalable testing method, and dynamic place-and-route. We summarize some of our own results in this area as well as those of others, and enumerate some future research directions required to make nanometer-scale computing a reality.