Power and performance evaluation of globally asynchronous locally synchronous processors
ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
CHARME '01 Proceedings of the 11th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
Automatic Production of Globally Asynchronous Locally Synchronous Systems
EMSOFT '02 Proceedings of the Second International Conference on Embedded Software
Power efficiency of voltage scaling in multiple clock, multiple voltage cores
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Efficient Self-Timed Interfaces for Crossing Clock Domains
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
Self-Timed Ring for Globally-Asynchronous Locally-Synchronous Systems
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
A critical analysis of application-adaptive multiple clock processors
Proceedings of the 2003 international symposium on Low power electronics and design
A mixed-clock issue queue design for globally asynchronous, locally synchronous processor cores
Proceedings of the 2003 international symposium on Low power electronics and design
Guaranteeing the quality of services in networks on chip
Networks on chip
TinyGALS: a programming model for event-driven embedded systems
Proceedings of the 2003 ACM symposium on Applied computing
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Reconfigurable platforms for ubiquitous computing
Proceedings of the 1st conference on Computing frontiers
Optimal partitioning of globally asychronous locally synchronous processor arrays
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Self-timed communication platform for implementing high-performance systems-on-chip
Integration, the VLSI Journal - Special issue: Networks on chip and reconfigurable fabrics
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
System level power and performance modeling of GALS point-to-point communication interfaces
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Toward a multiple clock/voltage island design style for power-aware processors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Synchro-Tokens: A Deterministic GALS Methodology for Chip-Level Debug and Test
IEEE Transactions on Computers
Speed and voltage selection for GALS systems based on voltage/frequency islands
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
An architecture and a wrapper synthesis approach for multi-clock latency-insensitive systems
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
A survey of research and practices of Network-on-chip
ACM Computing Surveys (CSUR)
Defect tolerance at the end of the roadmap
Nano, quantum and molecular computing
Hardware based frequency/voltage control of voltage frequency island systems
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
A real-time multimedia composition layer
Proceedings of the 1st ACM workshop on Audio and music computing multimedia
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Advanced hardware/software co-design on reconfigurable network-on-chip based hyper-platforms
Computers and Electrical Engineering
Design and DfT of a high-speed area-efficient embedded asynchronous FIFO
Proceedings of the conference on Design, automation and test in Europe
Test quality analysis and improvement for an embedded asynchronous FIFO
Proceedings of the conference on Design, automation and test in Europe
Voltage-frequency island partitioning for GALS-based networks-on-chip
Proceedings of the 44th annual Design Automation Conference
A predictive NoC architecture for vision systems dedicated to image analysis
EURASIP Journal on Embedded Systems
A Survey and Taxonomy of GALS Design Styles
IEEE Design & Test
Globally Asynchronous, Locally Synchronous Circuits: Overview and Outlook
IEEE Design & Test
Dynamic Voltage and Frequency Scaling Architecture for Units Integration within a GALS NoC
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
Integration, the VLSI Journal
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
Two-phase synchronization with sub-cycle latency
Integration, the VLSI Journal
Evolution in architectures and programming methodologies of coarse-grained reconfigurable computing
Microprocessors & Microsystems
Design and management of voltage-frequency island partitioned networks-on-chip
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power management of voltage/frequency island-based systems using hardware-based methods
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Multi-Clock Latency-Insensitive Architecture and Wrapper Synthesis
Electronic Notes in Theoretical Computer Science (ENTCS)
GALS Test Chip on 130nm Process
Electronic Notes in Theoretical Computer Science (ENTCS)
Low-power TinyOS tuned processor platform for wireless sensor network motes
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Proceedings of the 7th ACM international conference on Computing frontiers
Analysis and optimization of pausible clocking based GALS design
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
IEEE Transactions on Circuits and Systems Part I: Regular Papers
aelite: a flit-synchronous network on chip with composable and predictable services
Proceedings of the Conference on Design, Automation and Test in Europe
IEEE Transactions on Circuits and Systems Part I: Regular Papers
High rate data synchronization in GALS socs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power reduction of asynchronous logic circuits using activity detection
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 2011 SIGPLAN/SIGBED conference on Languages, compilers and tools for embedded systems
Power and area optimization of 3D networks-on-chip using smart and efficient vertical channels
PATMOS'11 Proceedings of the 21st international conference on Integrated circuit and system design: power and timing modeling, optimization, and simulation
Time aware modelling and analysis of multiclocked VLSI systems
ICFEM'06 Proceedings of the 8th international conference on Formal Methods and Software Engineering
Modeling and reducing EMI in GALS and synchronous systems
PATMOS'09 Proceedings of the 19th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
A novel hybrid FIFO asynchronous clock domain crossing interfacing method
Proceedings of the great lakes symposium on VLSI
VLSI implementation of a distributed algorithm for fault-tolerant clock generation
Journal of Electrical and Computer Engineering - Special issue on Clock/Frequency Generation Circuits and Systems
Robust evaluation of expressions by distributed virtual machines
UCNC'12 Proceedings of the 11th international conference on Unconventional Computation and Natural Computation
Developing a power-efficient and low-cost 3D NoC using smart GALS-based vertical channels
Journal of Computer and System Sciences
Exploring pausible clocking based GALS design for 40-nm system integration
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Low Power Two-Tier GALS Architecture for Multi Robot Collision Avoidance
Proceedings of Conference on Advances In Robotics
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In this paper we describe a complete design methodology for a globally asynchronous on-chip communication network connecting both locally synchronous and asynchronous modules. Synchronous modules are equipped with asynchronous wrappers, which adapt their interfaces to the self-timed environment and prevent meta-stability. These wrappers are assembled from a concise library of pre-designed technology-independent elements and provide high-speed data transfer. We confirmed the validity of our concept by applying it to an ASIC design implementing the Safer crypto-algorithm.