Robust interfaces for mixed-timing systems with application to latency-insensitive protocols
Proceedings of the 38th annual Design Automation Conference
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IEEE Micro
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ASYNC '00 Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems
ASYNC '01 Proceedings of the 7th International Symposium on Asynchronous Circuits and Systems
Efficient Self-Timed Interfaces for Crossing Clock Domains
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
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ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
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WVLSI '00 Proceedings of the IEEE Computer Society Annual Workshop on VLSI (WVLSI'00)
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ICCD '01 Proceedings of the International Conference on Computer Design: VLSI in Computers & Processors
Evaluation of pausible clocking for interfacing high speed IP cores in GALS Framework
VLSID '04 Proceedings of the 17th International Conference on VLSI Design
Generalized Latency-Insensitive Systems for Single-Clock and Multi-Clock Architectures
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Theory of latency-insensitive design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper presents an architecture and a wrapper synthesis approach for the design of multi-clock systems-on-chips. We build upon the initial work on multi-clock latency-insensitive systems by Singh and Theobald [Montek Singh and Michael Theobald. Generalized latency-insensitive systems for single-clock and multi-clock architectures. In Proc. Design, Automation and Test in Europe (DATE), February 2004], and provide a detailed system architecture with the following capabilities and benefits: (i) modules are stalled only when needed, thereby avoiding unnecessary stalling, (ii) adequate metastability resolution is provided, (iii) handshake interfaces between modules are high-performance and low-latency, i.e., capable of transfering data packets on every clock cycle, (iv) IP cores with large clock distribution delays are correctly handled, and (v) an automated approach is provided for wrapper synthesis from formal specifications. For wrapper synthesis, we chose the Component Wrapper Language (CWL) from Hitachi/Fujitsu [Fujitsu Ltd., Fujitsu Laboratories Ltd., and Hitachi Ltd. Component wrapper language. http://www.labs.fujitsu.com/en/techinfo/cwl/index.htm] as the specification language. Our synthesis approach has been implemented in a prototype tool. Synthesis results for a small set of examples are provided.