Fine-Grain Pipelined Asynchronous Adders for High-Speed DSP Applications

Authors:
Montek Singh;Steven M. Nowick
Affiliations:
-;-
Venue:
WVLSI '00 Proceedings of the IEEE Computer Society Annual Workshop on VLSI (WVLSI'00)
Year:
2000

Citing 0
Cited 7

A lattice-based framework for the classification and design of asynchronous pipelines

Proceedings of the 42nd annual Design Automation Conference
An asynchronous low-power high-performance sequential decoder implemented with QDI templates

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design and DfT of a high-speed area-efficient embedded asynchronous FIFO

Proceedings of the conference on Design, automation and test in Europe
MOUSETRAP: high-speed transition-signaling asynchronous pipelines

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
The design of high-performance dynamic asynchronous pipelines: high-capacity style

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Multi-Clock Latency-Insensitive Architecture and Wrapper Synthesis

Electronic Notes in Theoretical Computer Science (ENTCS)
An adaptively pipelined mixed synchronous-asynchronous digital FIR filter chip operating at 1.3 gigahertz

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Quantified Score

Hi-index	0.00

Visualization

Abstract

What should the students of today be learning and doing to prepare them for system design 10 years from now? What will be the biggest challenges facing them at that time? Then too, where are the biggest opportunities for research impact right now? To ...