Discrete-time signal processing
Discrete-time signal processing
Programming in VLSI: from communicating processes to delay-insensitive circuits
Developments in concurrency and communication
Self-timed rings and their application to division
Self-timed rings and their application to division
Energy-delay efficiency of VLSI computations
Proceedings of the 12th ACM Great Lakes symposium on VLSI
Computer Arithmetic: Principles, Architecture and Design
Computer Arithmetic: Principles, Architecture and Design
Predicting Performance of Micropipelines Using Charlie Diagrams
ASYNC '98 Proceedings of the 4th International Symposium on Advanced Research in Asynchronous Circuits and Systems
High-Throughput Asynchronous Pipelines for Fine-Grain Dynamic Datapaths
ASYNC '00 Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems
ASYNC '01 Proceedings of the 7th International Symposium on Asynchronous Circuits and Systems
ASYNC '02 Proceedings of the 8th International Symposium on Asynchronus Circuits and Systems
ASYNC '02 Proceedings of the 8th International Symposium on Asynchronus Circuits and Systems
The Design of an Asynchronous MIPS R3000 Microprocessor
ARVLSI '97 Proceedings of the 17th Conference on Advanced Research in VLSI (ARVLSI '97)
Fine-Grain Pipelined Asynchronous Adders for High-Speed DSP Applications
WVLSI '00 Proceedings of the IEEE Computer Society Annual Workshop on VLSI (WVLSI'00)
Design for Testability A Survey
IEEE Transactions on Computers
The design of high-performance dynamic asynchronous pipelines: lookahead style
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
The design of high-performance dynamic asynchronous pipelines: high-capacity style
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Application of partial-response channel coding to magnetic recording systems
IBM Journal of Research and Development
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A high-throughput low-latency digital finite impulse response (FIR) filter has been designed for use in partial-response maximum-likelihood (PRML) read channels of modern disk drives. The filter is a hybrid synchronous-asynchronous design. The speed-critical portion of the filter is designed as a high-performance asynchronous pipeline sandwiched between synchronous input and output portions, making it possible for the entire filter to be embedded within a clocked system. A novel feature of the filter is that the degree of pipelining is dynamically variable, depending upon the input data rate. This feature is critical in obtaining a very low filter latency throughout the range of operating frequencies. The filter is a ten-tap six-bit FIR filter, fabricated in a 0.18-µm CMOS process. Resulting chips were fully functional over a wide range of supply voltages, and exhibited throughputs of over 1.3 giga-items/s, and latencies of 2-5 clock cycles. Interestingly, the filter throughput was limited by the synchronous portion of the chip; the internal asynchronous pipeline was estimated to be capable of significantly higher throughputs, around 1.8 giga-items/s. More importantly though, the adaptively pipelined nature of the filter allows it to offer a worst-case latency of only 10 ns, which is half the worst-case latency of the best previously reported comparable fully-synchronous implementation by Rylov et al.