A New Control Circuit for Asynchronous Micropipelines
IEEE Transactions on Computers
Reducing probabilistic timed petri nets for asynchronous architectural analysis
Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems
Energy and Performance Models for Clocked and Asynchronous Communication
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
Designing an asynchronous microcontroller using pipefitter
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An architecture and a wrapper synthesis approach for multi-clock latency-insensitive systems
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
A survey of research and practices of Network-on-chip
ACM Computing Surveys (CSUR)
An asynchronous low-power high-performance sequential decoder implemented with QDI templates
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design and DfT of a high-speed area-efficient embedded asynchronous FIFO
Proceedings of the conference on Design, automation and test in Europe
Self-resetting latches for asynchronous micro-pipelines
Proceedings of the 44th annual Design Automation Conference
MOUSETRAP: high-speed transition-signaling asynchronous pipelines
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
The design of high-performance dynamic asynchronous pipelines: lookahead style
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
The design of high-performance dynamic asynchronous pipelines: high-capacity style
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An accelerator design for speedup of Java execution in consumer mobile devices
Computers and Electrical Engineering
Multi-Clock Latency-Insensitive Architecture and Wrapper Synthesis
Electronic Notes in Theoretical Computer Science (ENTCS)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Energy and performance models for synchronous and asynchronous communication
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Back annotation in high speed asynchronous design
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
| Hi-index | 0.00 |
This paper introduces several new asynchronous pipeline designs, which offer high throughput as well as low latency. The designs target dynamic datapaths, both dual-rail as well as single-rail. The new pipelines are latch-free and therefore are particularly well suited for fine-grain pipelining, i.e., where each pipeline stage is only a single gate deep. The pipelines employ new control structures and protocols aimed at reducing the handshaking delay, the principal impediment to achieving high throughput in asynchronous pipelines.As a test vehicle, a 4-bit FIFO was designed using 0.6-micron technology. The results of careful HSPICE simulations of the FIFO designs are very encouraging. The dual-rail designs deliver a throughput of up to 860 million data items per second. This performance represents an improvement by a factor of 2 over a widely used comparable approach by Williams. The new single-rail designs deliver a throughput of up to 1208 million data items per second.