Communications of the ACM
Handshake circuits: an asynchronous architecture for VLSI programming
Handshake circuits: an asynchronous architecture for VLSI programming
Peephole optimization of asynchronous macromodule networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
VLSI '93 Proceedings of the IFIP TC10/WG 10.5 International Conference on Very Large Scale Integration
Automated Synthesis of Micro-Pipelines from Behavioral Verilog HDL
ASYNC '00 Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Asynchronous Design Using Commercial HDL Synthesis Tools
ASYNC '00 Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems
High-Throughput Asynchronous Pipelines for Fine-Grain Dynamic Datapaths
ASYNC '00 Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Self-Calibrating Clocks for Globally Asynchronous Locally Synchronous Systems
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Globally-asynchronous locally-synchronous systems (performance, reliability, digital)
Globally-asynchronous locally-synchronous systems (performance, reliability, digital)
Modeling and synthesis of asynchronous pipelines
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper discusses how Pipefitter, a tool chain that implements a fully automated synthesis flow for asynchronous circuits, can be used to design a simple asynchronous microcontroller. The use of register transfer level (RTL)-like Verilog hardware description languages (HDL) as the input format makes the first steps of the design flow (i.e., specification and simulation) very easy for the designer. Pipefitter directly synthesizes the control unit as a hazard-free standard cell netlist, uses a genetic algorithm to perform binding and multiplexer optimization for the datapath and allows the user to manually specify the binding. It also produces a synthesizable Verilog specification for the datapath, as well as a set of scripts driving both its synthesis and timing analysis by state-of-the-art commercial synchronous RTL and logic synthesis tools. The automated insertion of matched delays completes the logic design, and hands off the netlist to the standard cell-based layout tools. The example presented in this brief, shows how Pipefitter can be effectively used for the design of asynchronous application specific integrated circuits.