Communicating sequential processes
Communicating sequential processes
Communications of the ACM
Programming in VLSI: from communicating processes to delay-insensitive circuits
Developments in concurrency and communication
Four-phase micropipeline latch control circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
High-level design for asynchronous logic
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Towards an energy complexity of computation
Information Processing Letters - Special issue in honor of Edsger W. Dijkstra
Design Challenges of Technology Scaling
IEEE Micro
Proceedings of the 40th annual Design Automation Conference
A single-rail re-implementation of a DCC error detector using a generic standard-cell library
ASYNC '95 Proceedings of the 2nd Working Conference on Asynchronous Design Methodologies
A Design Framework for Asynchronous/Synchronous Circuits Based on CHP to VHDL Translation
ASYNC '99 Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Reconfigurable Latch Controllers for Low Power Asynchronous Circuits
ASYNC '99 Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Designing an Asynchronous Bus Interface
ASYNC '01 Proceedings of the 7th International Symposium on Asynchronous Circuits and Systems
AMULET3: A High-Performance Self-Timed ARM Microprocessor
ICCD '98 Proceedings of the International Conference on Computer Design
The VLSI-programming language tangram and its translation into handshake circuits
EURO-DAC '91 Proceedings of the conference on European design automation
The best of both worlds: the efficient asynchronous implementation of synchronous specifications
Proceedings of the 41st annual Design Automation Conference
Designing an asynchronous microcontroller using pipefitter
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Attacking Control Overhead to Improve Synthesised Asynchronous Circuit Performance
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
A fully-automated desynchronization flow for synchronous circuits
Proceedings of the 44th annual Design Automation Conference
Automatic Compilation of Data-Driven Circuits
ASYNC '08 Proceedings of the 2008 14th IEEE International Symposium on Asynchronous Circuits and Systems
ASYNC '08 Proceedings of the 2008 14th IEEE International Symposium on Asynchronous Circuits and Systems
Desynchronization: Synthesis of Asynchronous Circuits From Synchronous Specifications
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Asynchronous Control Network Optimization Using Fast Minimum-Cycle-Time Analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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We propose a set of modeling rules and a synthesis method for the design of asynchronous pipelines. To keep the circuit area and power dissipation of the asynchronous control network small, the proposed approach avoids the conventional syntaxdirected translation approach. Instead, it employs a data-driven design style and a coarse-grain approach to the synthesis of asynchronous control, restricting asynchronous control to the implementation of communication channels commonly found in asynchronous pipelines and operations involving these channels. The proposed approach integrates well into conventional synchronous design flows because they are based on Verilog and System Verilog specifications, and generate register-transfer level models suitable for functional simulation and logic synthesis using existing computer-aided design tools. Using a 32-bit microprocessor, an interpolated finite-impulse-response filter bank, and a Reed-Solomon error detector as design examples, we show that the proposed approach is competitive with other comparable reported methods.