High-level design for asynchronous logic

Authors:
Ross Smith;Michiel Ligthart
Affiliations:
Theseus Logic;Theseus Logic
Venue:
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Year:
2001

Citing 1
Cited 1

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Abstract

Asynchronous, self-timed, logic is often eschewed in digital design because of its ad-hoc methodologies and lack of available design tools. This paper describes a complete High Level Design flow for asynchronous circuits based on Register Transfer Level (RTL) VHDL using commercial simulation and synthesis tools. Contrary to previous asynchronous approaches, the proposed RTL methodology closely resembles familiar synchronous design styles.