Asynchronous data-driven circuit synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Modeling and synthesis of asynchronous pipelines
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Several asynchronous system design tools are based on syntax-driven translation of behavioral specifications (e.g., Balsa, Haste). While they provide rapid design times, the performance of the resulting implementations is typically limited, in part because specifications written by designers often have limited concurrency due to unpipelined operation and unnecessary sequencing. To overcome these challenges, this paper proposes a "source-to-source'' transformation (i.e., code rewriting) of the original specification into a new one using a variety of concurrency-enhancing optimizations: (i) automatic parallelization, (ii) automatic pipelining, (iii) arithmetic optimization, and (iv) reordering of channel communication. Our approach has been integrated into an existing design flow, and applied to a suite of examples. Experimental results demonstrate that our approach correctly and efficiently rewrites the original specifications into highly concurrent ones. If code length is used as an indicator of designer effort, our approach reduces the required effort by a factor of 3.3x on average (up to 8.8x). Alternatively, the impact of our approach can be quantified by the throughput improvement achieved by optimizing the original specification: up to 59x speedup using our basic approach, and a further 5.2x using arithmetic optimization.