An energy-complexity model for VLSI computations
An energy-complexity model for VLSI computations
Towards an energy complexity of computation
Information Processing Letters - Special issue in honor of Edsger W. Dijkstra
Low Power Digital CMOS Design
ET2: a metric for time and energy efficiency of computation
Power aware computing
Energy-delay complexity of asychronous circuits
Energy-delay complexity of asychronous circuits
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Transistor sizing of energy-delay--efficient circuits
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power
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IBM Journal of Research and Development
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IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 11 - Volume 12
Power and performance optimization at the system level
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ICCD '05 Proceedings of the 2005 International Conference on Computer Design
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
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IEEE Transactions on Circuits and Systems Part I: Regular Papers
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Finding the energy efficient curve: gate sizing for minimum power under delay constraints
VLSI Design - Special issue on CAD for Gigascale SoC Design and Verification Solutions
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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HiPEAC'10 Proceedings of the 5th international conference on High Performance Embedded Architectures and Compilers
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ICPE '12 Proceedings of the 3rd ACM/SPEC International Conference on Performance Engineering
From energy-delay metrics to constraints on the design of digital circuits
International Journal of Circuit Theory and Applications
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In this paper we introduce an energy-delay efficiency metric that captures any trade-off between the energy and the delay of the computation.We apply this new concept to the parallel and sequential composition of circuits in general and in particular to circuits optimized through transistor sizing. We bound the delay and energy of the optimized circuit and we give necessary and sufficient conditions under which these bounds are reached. We also give necessary and sufficient conditions under which subcomponents of a design can be optimized independently so as to yield global optimum when recomposed.We demonstrate the utility of a minimum-energy function to capture high level compositional properties of circuits. The use of this minimum-energy function yields practical insight into ways of improving the overall energy-delay efficiency of circuits.