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DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Logic synthesis for low power VLSI designs
Logic synthesis for low power VLSI designs
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Logical effort: designing fast CMOS circuits
Logical effort: designing fast CMOS circuits
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Proceedings of the 12th ACM Great Lakes symposium on VLSI
Proceedings of the 2002 international symposium on Low power electronics and design
Convex Optimization
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IBM Journal of Research and Development
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Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems
High-Performance Energy-Efficient Microprocessor Design (Series on Integrated Circuits and Systems)
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Operations Research
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Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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A design scenario examined in this paper assumes that a circuit has been designed initially for high speed, and it is redesigned for low power by downsizing of the gates. In recent years, as power consumption has become a dominant issue, new optimizations of circuits are required for saving energy. This is done by trading off some speed in exchange for reduced power. For each feasible speed, an optimization problem is solved in this paper, finding new sizes for the gates such that the circuit satisfies the speed goal while dissipating minimal power. Energy/delay gain (EDG) is defined as a metric to quantify the most efficient tradeoff. The EDG of the circuit is evaluated for a range of reduced circuit speeds, and the power-optimal gate sizes are compared with the initial sizes. Most of the energy savings occur at the final stages of the circuits, while the largest relative downsizing occurs in middle stages. Typical tapering factors for power efficient circuits are larger than those for speed-optimal circuits. Signal activity and signal probability affect the optimal gate sizes in the combined optimization of speed and power.