On implementing addition in VLSI technology
Journal of Parallel and Distributed Computing
Logical effort: designing fast CMOS circuits
Logical effort: designing fast CMOS circuits
Proceedings of the 2002 international symposium on Low power electronics and design
Design Challenges of Technology Scaling
IEEE Micro
Energy-Delay Estimation Technique for High-Performance Microprocessor VLSI Adders
ARITH '03 Proceedings of the 16th IEEE Symposium on Computer Arithmetic (ARITH-16'03)
Balancing hardware intensity in microprocessor pipelines
IBM Journal of Research and Development
Comparison of high-performance VLSI adders in the energy-delay space
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Architectural Considerations for Energy Efficiency
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
HERQULES: system level cross-layer design exploration for efficient energy-quality trade-offs
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
General strategies to design nanometer flip-flops in the energy-delay space
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Finding the energy efficient curve: gate sizing for minimum power under delay constraints
VLSI Design - Special issue on CAD for Gigascale SoC Design and Verification Solutions
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Methodology for energy-efficient digital circuit sizing: important issues and design limitations
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Circuit sizing and supply-voltage selection for low-power digital circuit design
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Energy-delay space analysis for clocked storage elements under process variations
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
From energy-delay metrics to constraints on the design of digital circuits
International Journal of Circuit Theory and Applications
Logic style comparison for ultra low power operation in 65nm technology
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
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We present a systematic method for minimizing the energy of pipelined digital systems, through joint optimization of each pipeline stage and the system. A pipeline stage with a constant load can either be optimized for delay at a given input size, minimized for energy at a fixed delay, or have delay traded off for energy at a fixed input size. The results of these optimizations are combined to yield the design region for energy and delay. At the system level with a fixed throughput constraint, the sensitivities to input size and output load of all pipeline stages form the optimal energy criteria that provide a systematic method to minimize the total system energy. This method is applied to a media datapath, where we show up to 37% energy saving for a fixed performance. The minimal energy-delay curve of the system obtained through application of this method demonstrates similar characteristics as that of a single pipeline stage. With voltage scaling, the optimal solution displays a strong dependency between delay, energy, and supply voltage. The proper tradeoff between these entities makes a fundamental impact on efficient digital design.