Low power, testable dual edge triggered flip-flops
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
Logical effort: designing fast CMOS circuits
Logical effort: designing fast CMOS circuits
Towards an energy complexity of computation
Information Processing Letters - Special issue in honor of Edsger W. Dijkstra
Analysis and design of low-energy flip-flops
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Energy-delay efficiency of VLSI computations
Proceedings of the 12th ACM Great Lakes symposium on VLSI
Proceedings of the 2002 international symposium on Low power electronics and design
Introduction to VLSI Systems
Digital System Clocking: High-Performance and Low-Power Aspects
Digital System Clocking: High-Performance and Low-Power Aspects
Dynamic Flip-Flop with Improved Power
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Load-Sensitive Flip-Flop Characterization
WVLSI '01 Proceedings of the IEEE Computer Society Workshop on VLSI 2001
Clocking and clocked storage elements in a multi-gigahertz environment
IBM Journal of Research and Development
High-performance and low-power conditional discharge flip-flop
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Dual-edge triggered storage elements and clocking strategy for low-power systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Energy optimization of pipelined digital systems using circuit sizing and supply scaling
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
High-Performance Energy-Efficient Microprocessor Design (Series on Integrated Circuits and Systems)
High-Performance Energy-Efficient Microprocessor Design (Series on Integrated Circuits and Systems)
Activity-sensitive flip-flop and latch selection for reduced energy
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IC Mask Design
Flip-flop energy/performance versus clock slope and impact on the clock network design
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Noise constrained transistor sizing and power optimization for dual V/sub t/ domino logic
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Flip-flop energy/performance versus clock slope and impact on the clock network design
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Physical design aware comparison of flip-flops for high-speed energy-efficient VLSI circuits
PATMOS'10 Proceedings of the 20th international conference on Integrated circuit and system design: power and timing modeling, optimization and simulation
PATMOS'10 Proceedings of the 20th international conference on Integrated circuit and system design: power and timing modeling, optimization and simulation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
From energy-delay metrics to constraints on the design of digital circuits
International Journal of Circuit Theory and Applications
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In this paper, a general and complete design flow for nanometer flip-flops (FFs) is presented. The proposed design methodology permits to optimize FFs under constraints within the energy-delay space through extensive adoption of the Logical Effort method, which also allows for defining the bounds in the design space search. Transistors sizing is rigorously discussed by referring to cases that occur in practical designs. Appropriate metrics with clear physical meaning are proposed and various interesting properties are derived from circuit analysis. A well-defined design procedure is derived that can be easily automated with commercial CAD tools. In contrast to previous works, the impact of local interconnections is explicitly accounted for in the design loop, as is required in nanometer CMOS technologies. A case study is discussed in detail to exemplify the application of the proposed methodology. Extensive simulations for a typical FF in a 65-nm CMOS technology are presented to show the whole design procedure and validate the underlying assumptions.