Clocking and Clocked Storage Elements in Multi-GHz Environment
PATMOS '02 Proceedings of the 12th International Workshop on Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation
Clocking and clocked storage elements in a multi-gigahertz environment
IBM Journal of Research and Development
Jitter in Deep Sub-Micron Interconnect
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
Dual-edge triggered storage elements and clocking strategy for low-power systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A novel high-speed sense-amplifier-based flip-flop
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Energy Efficiency of Power-Gating in Low-Power Clocked Storage Elements
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
Flip-flop energy/performance versus clock slope and impact on the clock network design
IEEE Transactions on Circuits and Systems Part I: Regular Papers
General strategies to design nanometer flip-flops in the energy-delay space
IEEE Transactions on Circuits and Systems Part I: Regular Papers
HLS-l: high-level synthesis of high performance latch-based circuits
Proceedings of the Conference on Design, Automation and Test in Europe
Physical design aware comparison of flip-flops for high-speed energy-efficient VLSI circuits
PATMOS'10 Proceedings of the 20th international conference on Integrated circuit and system design: power and timing modeling, optimization and simulation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low-power soft error hardened latch
PATMOS'09 Proceedings of the 19th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Optimization of master-slave flip-flops for high-performance applications
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Low-power and high-speed design of a versatile bit-serial multiplier in finite fields GF(2m)
Integration, the VLSI Journal
The optimal fan-out of clock network for power minimization by adaptive gating
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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From the Publisher:Provides the only up-to-date source on the most recent advances in this often complex and fascinating topic.The only book to be entirely devoted to clockingClocking has become one of the most important topics in the field of digital system design.A "must have" book for advanced circuit engineers