Analysis and comparison in the energy-delay-area domain of nanometer CMOS flip-flops: part II-results and figures of merit

Authors:
Massimo Alioto;Elio Consoli;Gaetano Palumbo
Affiliations:
Dipartimento di Ingegneria dell'Informazione, Università di Siena, Siena, Italy and Berkeley Wireless Research Center-Electrical Engineering and Computer Science Department, University of Cal ...;Dipartimento di Ingegneria Elettrica, Elettronica e dei Sistemi, Università di Catania, Catania, Italy;Dipartimento di Ingegneria Elettrica, Elettronica e dei Sistemi, Università di Catania, Catania, Italy
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2011

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Abstract

In Part II of this paper, a comparison of the most representative flip-flop (FF) classes and topologies in a 65-nm CMOS technology is carried out. The comparison, which is performed on the energy-delay-area domain, exploits the strategies and methodologies for FFs analysis and design reported in Part I. In particular, the analysis accounts for the impact of leakage and layout parasitics on the optimization of the circuits. The tradeoffs between leakage, area, clock load, delay, and other interesting properties are extensively discussed. The investigation permits to derive several considerations on each FF class and to identify the best topologies for a targeted application.