A unified approach in the analysis of latches and flip-flops for low-power systems
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Conditional pre-charge techniques for power-efficient dual-edge clocking
Proceedings of the 2002 international symposium on Low power electronics and design
Low power integrated scan-retention mechanism
Proceedings of the 2002 international symposium on Low power electronics and design
Clocking and Clocked Storage Elements in Multi-GHz Environment
PATMOS '02 Proceedings of the 12th International Workshop on Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation
Level conversion for dual-supply systems
Proceedings of the 2003 international symposium on Low power electronics and design
Optimization of scannable latches for low energy
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power
Level conversion for dual-supply systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Clocking and clocked storage elements in a multi-gigahertz environment
IBM Journal of Research and Development
High-performance and low-power conditional discharge flip-flop
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
High performance level conversion for dual VDD design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Dual-edge triggered storage elements and clocking strategy for low-power systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low-overhead design of soft-error-tolerant scan flip-flops with enhanced-scan capability
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
A novel high-speed sense-amplifier-based flip-flop
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A 65-nm pulsed latch with a single clocked transistor
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Low-power clock branch sharing double-edge triggered flip-flop
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low Complexity Dual-Mode Pulse Generator Designs
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Conditional data mapping flip-flops for low-power and high-performance systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 46th Annual Design Automation Conference
Low-power clocked-pseudo-NMOS flip-flop for level conversion in dual supply systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Flip-flop energy/performance versus clock slope and impact on the clock network design
IEEE Transactions on Circuits and Systems Part I: Regular Papers
General strategies to design nanometer flip-flops in the energy-delay space
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Physical design aware comparison of flip-flops for high-speed energy-efficient VLSI circuits
PATMOS'10 Proceedings of the 20th international conference on Integrated circuit and system design: power and timing modeling, optimization and simulation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A robust edge encoding technique for energy-efficient multi-cycle interconnect
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design of sequential elements for low power clocking system
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low-power dual-edge triggered state retention scan flip-flop
PATMOS'09 Proceedings of the 19th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Energy-delay space analysis for clocked storage elements under process variations
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Low clock swing d flip-flops design by using output control and MTCMOS
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Timing-Error-Detecting Dual-Edge-Triggered Flip-Flop
Journal of Electronic Testing: Theory and Applications
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