Low-overhead design of soft-error-tolerant scan flip-flops with enhanced-scan capability

Authors:
Ashish Goel;Swarup Bhunia;Hamid Mahmoodi;Kaushik Roy
Affiliations:
Purdue University, West Lafayette, IN;Case Western Reserve University, Cleveland, OH;San Francisco State University, San Francisco, CA;Purdue University, West Lafayette, IN
Venue:
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Year:
2006

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Abstract

With technology scaling, soft error resilience is becoming a major concern in circuit design. This paper presents a class of low-overhead flip-flops suitable for soft error detection and correction. The proposed design reuses logic elements typically available in a standard-cell implementation of a flip-flop to reduce hardware overhead. We demonstrate that the proposed flip-flops are also suitable for enhanced scan based delay fault testing, which allows arbitrary two-pattern test application for the best combinational path testability. The proposed flip-flops show an average power reduction of 16% and area improvement of 17% compared to the best alternative techniques with no additional delay overhead.