A logic design structure for LSI testability
DAC '77 Proceedings of the 14th Design Automation Conference
Time Redundancy Based Soft-Error Tolerance to Rescue Nanometer Technologies
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Characterization of Soft Errors Caused by Single Event Upsets in CMOS Processes
IEEE Transactions on Dependable and Secure Computing
Analysis and design of soft-error hardened latches
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
A Low Power Soft Error Suppression Technique for Dynamic Logic
DFT '05 Proceedings of the 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Low-overhead design of soft-error-tolerant scan flip-flops with enhanced-scan capability
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Logic SER Reduction through Flipflop Redesign
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Time Redundancy Based Scan Flip-Flop Reuse To Reduce SER Of Combinational Logic
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Code Design for Dependable Systems: Theory and Practical Application
Code Design for Dependable Systems: Theory and Practical Application
VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon)
VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon)
Compact modeling of carbon nanotube transistor for early stage process-design exploration
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Circuit and Latch Capable of Masking Soft Errors with Schmitt Trigger
Journal of Electronic Testing: Theory and Applications
Soft Error Hardened FF Capable of Detecting Wide Error Pulse
DFT '08 Proceedings of the 2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems
SEU tolerant robust latch design
VDAT'12 Proceedings of the 16th international conference on Progress in VLSI Design and Test
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In recent high-density VLSIs, soft errors, particularly single event upsets (SEUs), frequently occur during system operation. In addition, the occurrence of delay faults caused by manufacturing defects is a significant problem. Thus, SEU tolerant design and delay fault testing are of increasing significance. This paper presents two types of SEU tolerant flip-flops (FFs). The proposed FFs tolerate SEUs caused by particles striking feedback loops in the FFs. Moreover, the proposed FFs allow enhanced scan delay fault testing. The proposed FFs are master-slave FFs, and the slave latches are constructed by modifying existing SEU tolerant latches, namely, SEH latches. The two proposed FFs tolerate particles with charges of 370 fC and of 369 fC or lower, whereas an existing SEU tolerant enhanced scan FF, called an ESFF-SEC, tolerates those of 431 fC or lower. Furthermore, the areas of the proposed FFs are 23.1% and 20.5% smaller than that of the ESFF-SEC. The CK-Q delay times are 44.4% and 41.1% shorter than that of the ESFF-SEC. Moreover, the average power consumptions of the proposed FFs during system operations are 55.6% and 53.3% lower than that of the ESFF-SEC.