Latch Design for Transient Pulse Tolerance
ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Characterization of Soft Errors Caused by Single Event Upsets in CMOS Processes
IEEE Transactions on Dependable and Secure Computing
A Highly-Efficient Technique for Reducing Soft Errors in Static CMOS Circuits
ICCD '04 Proceedings of the IEEE International Conference on Computer Design
Logic soft errors in sub-65nm technologies design and CAD challenges
Proceedings of the 42nd annual Design Automation Conference
Soft error reduction in combinational logic using gate resizing and flipflop selection
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Task scheduling for reliable cache architectures of multiprocessor systems
Proceedings of the conference on Design, automation and test in Europe
Circuit optimization techniques to mitigate the effects of soft errors in combinational logic
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Construction of SEU tolerant flip-flops allowing enhanced scan delay fault testing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Methods for fault tolerance in networks-on-chip
ACM Computing Surveys (CSUR)
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With technology scaling, combinational logic is becoming increasingly vulnerable to radiation strikes. Classical fault tolerant techniques mainly address Single Even Upsets (SEUs). Robust combinational logic designs capable of tolerating Single Event Transients (SETs) also are needed in lower technology nodes. In this paper, we present a novel SET mitigation scheme for flip-flops based on the time redundancy principle. The incurred area overhead due to the radiation hardening is minimized by reusing existing components (uses existing scan portion for SET tolerance). As shown by the simulation results, the proposed SET tolerant flip-flop has no performance overheads and simulation results that show the area overheads in ISCAS benchmark circuits are also presented.