Analysis and design of soft-error hardened latches
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Time Redundancy Based Scan Flip-Flop Reuse To Reduce SER Of Combinational Logic
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Design at high level of a robust 8-bit microprocessor to soft errors by using only standard gates
SBCCI '06 Proceedings of the 19th annual symposium on Integrated circuits and systems design
Soft error rate reduction using redundancy addition and removal
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
A case study in reliability-aware design: a resilient LDPC code decoder
Proceedings of the conference on Design, automation and test in Europe
A low-overhead and reliable switch architecture for Network-on-Chips
Integration, the VLSI Journal
Soft error modeling and remediation techniques in ASIC designs
Microelectronics Journal
Error immune logic for low-power probabilistic computing
VLSI Design - Special issue on selected papers from the midwest symposium on circuits and systems
A rapid prototyping system for error-resilient multi-processor systems-on-chip
Proceedings of the Conference on Design, Automation and Test in Europe
Characterizing the impact of soft errors on iterative methods in scientific computing
Proceedings of the international conference on Supercomputing
SC '12 Proceedings of the International Conference on High Performance Computing, Networking, Storage and Analysis
A low-cost, systematic methodology for soft error robustness of logic circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Soft errors are functional failures resulting from the latching of single-event transients (transient voltage fluctuations at a logic node or SETs) caused by high-energy particle strikes or electrical noise. Traditionally, they have been deemed to be a problem in memory structures, for which effective techniques (such as error correcting codes) are well known. However, due to technology scaling and reduced supply voltages, they are expected to increase by several orders of magnitude in logic circuits. Existing circuit and architectural approaches to addressing soft errors in logic circuits have appreciable area/cost, performance, and/or energy overheads or are limited to particular types of circuits (combinational or sequential). We present a very efficient and systematic error masking technique that uses the same circuitry to cope with soft errors in combinational and sequential circuits. It prevents an SET pulse of width less than approximately half of the slack available in the propagation path from latching and turning into a soft error. The SET is masked without additional delay and within the clock cycle time in an area- and energy-efficient manner, which makes this technique attractive for commodity as well as reliability-critical applications. Our technique also tolerates soft errors in the overhead circuitry, which we minimize through clustering. Application of our technique to ISCAS85 benchmark circuits yields an average SER reduction of 70.93% with an average area overhead of only 11.98%.