Design at high level of a robust 8-bit microprocessor to soft errors by using only standard gates

Authors:
Rodrigo Possamai Bastos;Fernanda Lima Kastensmidt;Ricardo Reis
Affiliations:
Universidade Federal do Rio Grande do Sul (UFRGS), Porto Alegre, RS, Brazil;Universidade Federal do Rio Grande do Sul (UFRGS), Porto Alegre, RS, Brazil;Universidade Federal do Rio Grande do Sul (UFRGS), Porto Alegre, RS, Brazil
Venue:
SBCCI '06 Proceedings of the 19th annual symposium on Integrated circuits and systems design
Year:
2006

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Abstract

This work presents a fault-tolerant IC version of a mass-produced 8-bit microprocessor from the M68HC11 family. It is able to tolerate Single Event Transients (SETs) and Single Event Upsets (SEUs). Based on the Triple Modular Redundancy (TMR) and Time Redundancy (TR) fault tolerance techniques, a protection scheme was designed and implemented at high level in the target microprocessor by using only standard logic gates. A typical IC design flow was developed by means of commercial CAD tools. Functional testing and fault injection simulations through benchmark executions were performed as a design verification testing. Furthermore, fault-tolerant IC design issues and results in area, performance and power were compared with a non-protected microprocessor version.