The design of a SRAM-based field-programmable gate array—part II: circuit design and layout
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Switching and Finite Automata Theory: Computer Science Series
Switching and Finite Automata Theory: Computer Science Series
A fault injection environment for microprocessor-based boards
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Prototyping and reengineering of microcontroller-based systems
RSP '96 Proceedings of the 7th IEEE International Workshop on Rapid System Prototyping (RSP '96)
Implementing a self-testing 8051 microprocessor
SBCCI'99 Proceedings of the XIIth conference on Integrated circuits and systems design
Design at high level of a robust 8-bit microprocessor to soft errors by using only standard gates
SBCCI '06 Proceedings of the 19th annual symposium on Integrated circuits and systems design
Functionally Fault-tolerant DSP Microprocessor using Sigma---delta Modulated Signals
Journal of Electronic Testing: Theory and Applications
Design of a soft-error robust microprocessor
Microelectronics Journal
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This paper presents the implementation of a fault detection and correction technique used to design a robust 8051 micro-controller with respect to a particular transient fault called Single Event Upset (SEU). A specific study regarding the effects of a SEU in the micro-controller behavior was performed. Furthermore, a fault tolerant technique was implemented in a version of the 8051. The VHDL description of the fault-tolerant microprocessor was prototyped in a FPGA environment and results in terms of area overhead, level of protection and performance penalties are discussed.