Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
Synthesis of an 8051-Like Micro-Controller Tolerant to Transient Faults
Journal of Electronic Testing: Theory and Applications
Analog Signal Generation for Built-in-Self-Test of Mixed-Signal Integrated Circuits
Analog Signal Generation for Built-in-Self-Test of Mixed-Signal Integrated Circuits
Evaluation of a Soft Error Tolerance Technique Based on Time and/or Space Redundancy
SBCCI '00 Proceedings of the 13th symposium on Integrated circuits and systems design
A Tutorial on Reed-Solomon Coding for Fault-Tolerance in RAID-likeSystems
A Tutorial on Reed-Solomon Coding for Fault-Tolerance in RAID-likeSystems
Defect and Error Tolerance in the Presence of Massive Numbers of Defects
IEEE Design & Test
Arithmetic Operators Robust to Multiple Simultaneous Upsets
DFT '04 Proceedings of the Defect and Fault Tolerance in VLSI Systems, 19th IEEE International Symposium
Designing logic circuits for probabilistic computation in the presence of noise
Proceedings of the 42nd annual Design Automation Conference
Increasing Fault Tolerance to Multiple Upsets Using Digital Sigma-Delta Modulators
IOLTS '05 Proceedings of the 11th IEEE International On-Line Testing Symposium
Reliable Digital Circuits Design using Sigma-Delta Modulated Signals
DFT '05 Proceedings of the 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Evaluating Sigma-Delta Modulated Signals to Develop Fault-Tolerant Circuits
ETS '06 Proceedings of the Eleventh IEEE European Test Symposium
Fully parallel stochastic computation architecture
IEEE Transactions on Signal Processing
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The occurrence of soft-faults in digital circuits due to single event upsets (SEU) caused by particle hits has been reported in many works, and it has been claimed that, as the transistor dimensions shrink, multiple and simultaneous faults will be a common scenario in future technologies. Many techniques have been proposed to cope with these kinds of faults, most of them based on hardware or software redundancy. In this work, we present a new paradigm, which is based on signal redundancy, that is, the signal to be processed will contain a certain amount of redundancy, in such a way that, even under the occurrence of multiple faults, the final results will sustain a good resolution for some applications. A DSP microprocessor that uses the technique was prototyped, and some results are presented and compared to typical n-bits binary coded DSP microprocessor architecture, showing the advantages of using the proposed approach.