Going beyond TMR for protection against multiple faults
SBCCI '05 Proceedings of the 18th annual symposium on Integrated circuits and system design
Functionally Fault-tolerant DSP Microprocessor using Sigma---delta Modulated Signals
Journal of Electronic Testing: Theory and Applications
A probabilistic LDPC-coded fault compensation technique for reliable nanoscale computing
IEEE Transactions on Circuits and Systems II: Express Briefs
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Future technologies, below 90nm, will present transistors so small that they will be heavily influenced by electromagnetic noise and SEU induced errors. This way, together with process variability, design as known today is likely to change. Since many soft errors might appear at the same time, a different design approach must be taken. The use of inherently robust operators as an alternative to conventional digital arithmetic operators is proposed in this study. The behavior of the proposed operators is analyzed through the simulation of single and multiple random faults injection, and it is shown to be adequate for several classes of applications, standing to multiple simultaneous upsets. The number of tolerated upsets varies according to the number of extra bits appended to the operands, and is limited only by the area restriction. For example, in a multiplier with 2 extra bits per operand, one can obtain robustness against up to 15 simultaneous faults.