Going beyond TMR for protection against multiple faults

Authors:
C. A. L. Lisbôa;E. Schüler;Luigi Carro
Affiliations:
Universidade Federal do Rio Grande do Sul, Porto Alegre, Brasil;Universidade Federal do Rio Grande do Sul, Porto Alegre, Brasil;Universidade Federal do Rio Grande do Sul, Porto Alegre, Brasil
Venue:
SBCCI '05 Proceedings of the 18th annual symposium on Integrated circuits and system design
Year:
2005

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Abstract

Future technologies will present devices so small that they will be heavily influenced by electromagnetic noise and SEU induced errors. Since many soft errors might appear at the same time, classical fault tolerance techniques, such as TMR, will no longer provide reliable protection and will make new design approaches necessary. This study shows that the TMR approach has intrinsic weaknesses that impair its effectiveness in the presence of multiple faults, and proposes a new technique that provides better protection than TMR for single as well as multiple faults. The proposed technique is based on the use of some analog components among the digital circuits. We present results based on a multiplier, and show that the technique is scalable to withstand higher quantities of simultaneous faults.