Reducing pin and area overhead in fault-tolerant FPGA-based designs
FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
Designing fault tolerant systems into SRAM-based FPGAs
Proceedings of the 40th annual Design Automation Conference
Designing and testing fault-tolerant techniques for SRAM-based FPGAs
Proceedings of the 1st conference on Computing frontiers
Simulating Single Event Transients in VDSM ICs for Ground Level Radiation
Journal of Electronic Testing: Theory and Applications
Susceptibility of Commodity Systems and Software to Memory Soft Errors
IEEE Transactions on Computers
Gate-Level Mitigation Techniques for Neutron-Induced Soft Error Rate
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
SBCCI '05 Proceedings of the 18th annual symposium on Integrated circuits and system design
Going beyond TMR for protection against multiple faults
SBCCI '05 Proceedings of the 18th annual symposium on Integrated circuits and system design
Energy-efficient soft error-tolerant digital signal processing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design at high level of a robust 8-bit microprocessor to soft errors by using only standard gates
SBCCI '06 Proceedings of the 19th annual symposium on Integrated circuits and systems design
Functionally Fault-tolerant DSP Microprocessor using Sigma---delta Modulated Signals
Journal of Electronic Testing: Theory and Applications
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
A delay-efficient radiation-hard digital design approach using CWSP elements
Proceedings of the conference on Design, automation and test in Europe
Fault-tolerant semantic mappings among heterogeneous and distributed local ontologies
Proceedings of the 2nd international workshop on Ontologies and information systems for the semantic web
Efficient analytical determination of the SEU-induced pulse shape
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Design of a soft-error robust microprocessor
Microelectronics Journal
Design of self correcting radiation hardened digital circuits using decoupled ground bus
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Evaluating the effectiveness of a mixed-signal TMR scheme based on design diversity
SBCCI '10 Proceedings of the 23rd symposium on Integrated circuits and system design
Design of the coarse-grained reconfigurable architecture DART with on-line error detection
Microprocessors & Microsystems
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IC technologies are approaching the ultimate limits of silicon in terms of channel width, power supply and speed. By approaching these limits, circuits are becoming increasingly sensitive to noise, which will result in unacceptable rates of soft-errors. Manufacturing testing and periodic testing cannot cope with soft errors. Thus, fault tolerant techniques will become necessary even for commodity applications. This work considers the implementation of a new soft error tolerance technique based on time redundancy. Arithmetic circuits were used as test vehicle to validate the approach. Simulations and performance evaluation of the proposed fault-tolerance technique were made using in-house tools realized around an event driven simulator. The obtained results show that tolerance of soft errors can be achieved at low cost.