Design and Analysis of an Optimal Instruction-Retry Policy for TMR Controller Computers
IEEE Transactions on Computers
Evaluation of a Soft Error Tolerance Technique Based on Time and/or Space Redundancy
SBCCI '00 Proceedings of the 13th symposium on Integrated circuits and systems design
Energy-Efficient Duplex and TMR Real-Time Systems
RTSS '02 Proceedings of the 23rd IEEE Real-Time Systems Symposium
A Design Diversity Metric and Reliability Analysis for Redundant Systems
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Designing Fault-Tolerant Techniques for SRAM-Based FPGAs
IEEE Design & Test
Energy-efficient soft error-tolerant digital signal processing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Radiation Effects on Embedded Systems
Radiation Effects on Embedded Systems
Single Event Upset: An Embedded Tutorial
VLSID '08 Proceedings of the 21st International Conference on VLSI Design
Using TMR Architectures for Yield Improvement
DFT '08 Proceedings of the 2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems
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This paper explores the concept of design diversity redundancy applied to mixed-signal (MS) circuit blocks, as a proposal to increase system reliability. Three different implementations of a second order low-pass filter (which perform the same transfer function) associated to a majority voter are used to build a diversity TMR scheme. The whole system is prototyped by using a single programmable mixed-signal device. Functional verifications and a fault injection campaign are performed, and the effectiveness of the voting system to detect single faults is investigated. Based on these results, analytical calculations were done to estimate the behavior of the system under the occurrence of double faults. Results show a very good ability of the system to tolerate double faults from the considered model.