Discrete-time signal processing
Discrete-time signal processing
Noise in deep submicron digital design
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Technology and design challenges for low power and high performance
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
DIVA: a reliable substrate for deep submicron microarchitecture design
Proceedings of the 32nd annual ACM/IEEE international symposium on Microarchitecture
Reliable low-power design in the presence of deep submicron noise (embedded tutorial session)
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Soft digital signal processing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
Exploiting Redundancy to Speed Up Parallel Systems
IEEE Parallel & Distributed Technology: Systems & Technology
A Time Redundancy Approach to TMR Failures Using Fault-State Likelihoods
IEEE Transactions on Computers
REESE: A Method of Soft Error Detection in Microprocessors
DSN '01 Proceedings of the 2001 International Conference on Dependable Systems and Networks (formerly: FTCS)
Modeling the Effect of Technology Trends on the Soft Error Rate of Combinational Logic
DSN '02 Proceedings of the 2002 International Conference on Dependable Systems and Networks
Evaluation of a Soft Error Tolerance Technique Based on Time and/or Space Redundancy
SBCCI '00 Proceedings of the 13th symposium on Integrated circuits and systems design
Self-Checking Circuits versus Realistic Faults in Very Deep Submicron
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Concurrent Detection of Soft Errors Based on Current Monitoring
IOLTW '01 Proceedings of the Seventh International On-Line Testing Workshop
Reliable low-power digital signal processing via reduced precision redundancy
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A soft error rate analysis (SERA) methodology
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Low-power filtering via adaptive error-cancellation
IEEE Transactions on Signal Processing
Fault Tolerance Analysis of Communication System Interleavers: the 802.11a Case Study
Journal of Signal Processing Systems
Integration, the VLSI Journal
Outstanding research problems in NoC design: system, microarchitecture, and circuit perspectives
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Checksum-based probabilistic transient-error compensation for linear digital systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Fault tolerance in transform-domain adaptive filters operating with real-valued signals
IEEE Transactions on Circuits and Systems Part I: Regular Papers
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Evaluating the effectiveness of a mixed-signal TMR scheme based on design diversity
SBCCI '10 Proceedings of the 23rd symposium on Integrated circuits and system design
Efficient soft error-tolerant adaptive equalizers
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Reduced-precision redundancy on FPGAs
International Journal of Reconfigurable Computing
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In this paper, we present energy-efficient soft error-tolerant techniques for digital signal processing (DSP) systems. The proposed technique, referred to as algorithmic soft error-tolerance (ASET), employs low-complexity estimators of a main DSP block to achieve reliable operation in the presence of soft errors. Three distinct ASET techniques-spatial, temporal and spatio-temporal-are presented. For frequency selective finite-impulse response (FIR) filtering, it is shown that the proposed techniques provide robustness in the presence of soft error rates of up to Per = 10-2 and Per = 10-3 in a single-event upset scenario. The power dissipation of the proposed techniques ranges from 1.1 X to 1.7 X (spatial ASET) and 1.05 X to 1.17 X (spatio-temporal and temporal ASET) when the desired signal-to-noise ratio SNRdes : 25 dB. In comparison, the power dissipation of the commonly employed triple modular redundancy technique is 2.9 X.