Design of Self-Checking Circuits Using DCVS Logic: A Case Study
IEEE Transactions on Computers
Cost reduction and evaluation of temporary faults detecting technique
DATE '00 Proceedings of the conference on Design, automation and test in Europe
The Future of Systems Research
Computer
Design Challenges of Technology Scaling
IEEE Micro
IEEE Transactions on Computers
Soft-Error Detection through Software Fault-Tolerance Techniques
DFT '99 Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems
Fault Tolerance through Re-Execution in Multiscalar Architecture
DSN '00 Proceedings of the 2000 International Conference on Dependable Systems and Networks (formerly FTCS-30 and DCCA-8)
A study of time redundant fault tolerance techniques for superscalar processors
DFT '95 Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
G4: A Fault-Tolerant CMOS Mainframe
FTCS '98 Proceedings of the The Twenty-Eighth Annual International Symposium on Fault-Tolerant Computing
AR-SMT: A Microarchitectural Approach to Fault Tolerance in Microprocessors
FTCS '99 Proceedings of the Twenty-Ninth Annual International Symposium on Fault-Tolerant Computing
Incorporating fault tolerance in superscalar processors
HIPC '96 Proceedings of the Third International Conference on High-Performance Computing (HiPC '96)
Time Redundancy Based Soft-Error Tolerance to Rescue Nanometer Technologies
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Self-Checking Circuits versus Realistic Faults in Very Deep Submicron
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Concurrent Error Detection in ALU's by Recomputing with Shifted Operands
IEEE Transactions on Computers
Fault-Tolerant Microprocessor-Based Systems
IEEE Micro
A Watchdog Processor Architecture with Minimal Performance Overhead
SAFECOMP '02 Proceedings of the 21st International Conference on Computer Safety, Reliability and Security
Energy-efficient soft error-tolerant digital signal processing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Specification and design considerations for reliable embedded systems
Proceedings of the conference on Design, automation and test in Europe
Datapath error detection with no detection latency for high-performance microprocessors
WSEAS Transactions on Computers
Sequential element design with built-in soft error resilience
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Reliable data path design of VLIW processor cores with comprehensive error-coverage assessment
Microprocessors & Microsystems
Fault-Tolerant VLIW processor design and error coverage analysis
EUC'06 Proceedings of the 2006 international conference on Embedded and Ubiquitous Computing
Configurable fault-tolerance for a configurable VLIW processor
ARC'13 Proceedings of the 9th international conference on Reconfigurable Computing: architectures, tools, and applications
A survey of checker architectures
ACM Computing Surveys (CSUR)
Journal of Electronic Testing: Theory and Applications
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Abstract: Future reliability of general-purpose processors (GPPs) is threatened by a combination of shrinking transistor size, higher clock rates, reduced supply voltages, and other factors. It is predicted that the occurrence of arbitrary transient faults, or soft errors, will dramatically increase as these trends continue. In this paper, we develop and evaluate a fault-tolerant microprocessor architecture that detects soft errors in its own data pipeline. This architecture accomplishes soft error detection through time redundancy, while requiring little execution time overhead. Our approach, called REESE (REdundant Execution using Spare Elements), first minimizes this overhead and then decreases it even further by strategically adding a small number of functional units to the pipeline. This differs from similar approaches in the past that have not addressed ways of reducing the overhead necessary to implement time redundancy in GPPs.