Systematic Unidirectional Error-Detecting Codes
IEEE Transactions on Computers
Design & analysis of fault tolerant digital systems
Design & analysis of fault tolerant digital systems
Self-checking and fault-tolerant digital design
Self-checking and fault-tolerant digital design
Computer
Fault Injection Techniques and Tools
Computer
Fault-Secure Parity Prediction Arithmetic Operators
IEEE Design & Test
Soft-Error Detection through Software Fault-Tolerance Techniques
DFT '99 Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems
REESE: A Method of Soft Error Detection in Microprocessors
DSN '01 Proceedings of the 2001 International Conference on Dependable Systems and Networks (formerly: FTCS)
Comparison and Application of Different VHDL-Based Fault Injection Techniques
DFT '01 Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
Modeling the Effect of Technology Trends on the Soft Error Rate of Combinational Logic
DSN '02 Proceedings of the 2002 International Conference on Dependable Systems and Networks
A study of time redundant fault tolerance techniques for superscalar processors
DFT '95 Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
AR-SMT: A Microarchitectural Approach to Fault Tolerance in Microprocessors
FTCS '99 Proceedings of the Twenty-Ninth Annual International Symposium on Fault-Tolerant Computing
SSD: An Affordable Fault Tolerant Architecture for Superscalar Processors
PRDC '01 Proceedings of the 2001 Pacific Rim International Symposium on Dependable Computing
Basic Concepts and Taxonomy of Dependable and Secure Computing
IEEE Transactions on Dependable and Secure Computing
Characterization of Soft Errors Caused by Single Event Upsets in CMOS Processes
IEEE Transactions on Dependable and Secure Computing
Microarchitecture-Based Introspection: A Technique for Transient-Fault Tolerance in Microprocessors
DSN '05 Proceedings of the 2005 International Conference on Dependable Systems and Networks
Microprocessor Sensitivity to Failures: Control vs Execution and Combinational vs Sequential Logic
DSN '05 Proceedings of the 2005 International Conference on Dependable Systems and Networks
Concurrent Detection of Control Flow Errors by Hybrid Signature Monitoring
IEEE Transactions on Computers
Multiple Transient Faults in Logic: An Issue for Next Generation ICs
DFT '05 Proceedings of the 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Diagnosis and repair method of SoC memory
WSEAS Transactions on Circuits and Systems
Algebra-logical diagnosis model for SoC F-IP
WSEAS Transactions on Circuits and Systems
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Error detection plays an important role in fault-tolerant computer systems. Two primary parameters concerned for error detection are the coverage and latency. In this paper, a new, hybrid error-detection approach offering a very high coverage with zero detection latency is proposed to protect the data paths of high-performance microprocessors. The feature of zero detection latency is essential to real-time error recovery. The hybrid error-detection approach is to combine the duplication with comparison, tripcle modular redundancy (TMR) and self-checking mechanisms to construct a formal framework, which allows the error-detection schemes of varying hardware complexity, performance and error-detection coverage to be incorporated. An experimental 32-bit VLIW core was employed to demonstrate the concept of hybrid detection approach. The hardware implementations in VHDL and simulated fault injection experiments were conducted to measure the interesting design metrics, such as hardware overhead, performance degradation and error-detection coverage.