Using Abstraction for Efficient Formal Verification of Pipelined Processors with Value Prediction
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Datapath error detection with no detection latency for high-performance microprocessors
WSEAS Transactions on Computers
Fault-Tolerant VLIW processor design and error coverage analysis
EUC'06 Proceedings of the 2006 international conference on Embedded and Ubiquitous Computing
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This paper proposes an integrity checking architecturefor superscalar processors that can achieve fault tolerancecapability of a duplex system at much less cost thanthe traditional duplication approach.The pipeline of theCPU core (P-pipeline) is combined in series with anotherpipeline (V-pipeline), which re-executes instructions processedin the P-pipeline.Operations in the two pipelines arecompared and any mismatch triggers recovery process. TheV-pipeline design is based on replication of the P-pipeline,and minimized in size and functionality by taking advantageof control flow and data dependency resolved in theP-pipeline.Idle cycles propagated from the P-pipeline becomeextra time for the V-pipeline to keep up with programre-execution.For a large-scale superscalar processor, theproposed architecture can bring up to 61.4% reduction indie area and the average execution time increase is 0.3%.