A watchdog processor based general rollback technique with multiple retries
IEEE Transactions on Software Engineering
Processor Control Flow Monitoring Using Signatured Instruction Streams
IEEE Transactions on Computers
Optimal checkpointing of real-time tasks
IEEE Transactions on Computers
Checkpoint repair for high-performance out-of-order execution machines
IEEE Transactions on Computers
Spare Capacity as a Means of Fault Detection and Diagnosis in Multiprocessor Systems
IEEE Transactions on Computers
Concurrent Error Detection Using Watchdog Processors-A Survey
IEEE Transactions on Computers
Exploiting Instruction-Level Parallelism for Integrated Control-Flow Monitoring
IEEE Transactions on Computers
Concurrent Error Detection in Multiply and Divide Arrays
IEEE Transactions on Computers
Fault Detection Capabilities of Alternating Logic
IEEE Transactions on Computers
Dual use of superscalar datapath for transient-fault detection and recovery
Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture
REESE: A Method of Soft Error Detection in Microprocessors
DSN '01 Proceedings of the 2001 International Conference on Dependable Systems and Networks (formerly: FTCS)
Hierarchical Verification for Increasing Performance in Reliable Processors
Journal of Electronic Testing: Theory and Applications
Datapath error detection with no detection latency for high-performance microprocessors
WSEAS Transactions on Computers
Instruction-Level Fault Tolerance Configurability
Journal of Signal Processing Systems
Reliable data path design of VLIW processor cores with comprehensive error-coverage assessment
Microprocessors & Microsystems
Protective redundancy overhead reduction using instruction vulnerability factor
Proceedings of the 7th ACM international conference on Computing frontiers
Proceedings of the Conference on Design, Automation and Test in Europe
Instruction precomputation with memoization for fault detection
Proceedings of the Conference on Design, Automation and Test in Europe
Fault-Tolerant VLIW processor design and error coverage analysis
EUC'06 Proceedings of the 2006 international conference on Embedded and Ubiquitous Computing
Configurable fault-tolerance for a configurable VLIW processor
ARC'13 Proceedings of the 9th international conference on Reconfigurable Computing: architectures, tools, and applications
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As more and more transistors are incorporated into processor chips, the circuits are becoming more and more error-prone, necessitating the introduction of fault tolerance techniques. This paper investigates techniques to incorporate fault tolerance in superscalar processors by exploiting the functional unit redundancy available in these processors. The schemes investigated in this paper do not require any modifications to the instruction set architecture of the machine, and no additional instructions are added by the compiler. The paper also presents the results of a simulation study that we conducted to analyze the performance impact of the investigated fault tolerance schemes.