Lx: a technology platform for customizable VLIW embedded processing
Proceedings of the 27th annual international symposium on Computer architecture
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IEEE Transactions on Computers - Special issue on fault-tolerant embedded systems
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DSN '00 Proceedings of the 2000 International Conference on Dependable Systems and Networks (formerly FTCS-30 and DCCA-8)
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DSN '01 Proceedings of the 2001 International Conference on Dependable Systems and Networks (formerly: FTCS)
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DSN '02 Proceedings of the 2002 International Conference on Dependable Systems and Networks
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DFT '95 Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
Evaluating Low-Cost Fault-Tolerance Mechanism for Microprocessors on Multimedia Applications
PRDC '01 Proceedings of the 2001 Pacific Rim International Symposium on Dependable Computing
Compiler-Directed Instruction Duplication for Soft Error Detection
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
SCS '06 Proceedings of the eleventh Australian workshop on Safety critical systems and software - Volume 69
Study of the Effects of SEU-Induced Faults on a Pipeline Protected Microprocessor
IEEE Transactions on Computers
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ARC '09 Proceedings of the 5th International Workshop on Reconfigurable Computing: Architectures, Tools and Applications
Reliable data path design of VLIW processor cores with comprehensive error-coverage assessment
Microprocessors & Microsystems
Combining Hardware- and Software-Based Self-Repair Methods for Statically Scheduled Data Paths
DFT '10 Proceedings of the 2010 IEEE 25th International Symposium on Defect and Fault Tolerance in VLSI Systems
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This paper presents the design and implementation of configurable fault-tolerance techniques for a configurable VLIW processor. The processor can be configured for 2, 4, or 8 issue-slots with different types of execution functional units (FUs), and its instruction set architecture (ISA) is based on the VEX ISA. Separate techniques are employed to protect different modules of the processor from single event upsets (SEU) errors. Parity checking is utilized to detect errors in the instruction and data memories and the general register file (GR), while triple modular redundancy (TMR) approach is employed for all the synchronous flip-flops (FFs). At design-time, a user can choose between the standard non fault-tolerant design, a fault-tolerant design where the fault tolerance is permanently enabled, and a fault-tolerant design where the fault tolerance can be enabled and disabled at run-time. These options enable a user to trade-off between hardware resources, performance, and power consumption. A simulation based technique is utilized for testing purposes. The processor is implemented in a Xilinx Virtex-6 FPGA as well as synthesized to a 90 nm ASIC technology. Compared to the permanently enabled fault-tolerance, in scenarios, where fault-tolerance is not required at some point in time, considerable power savings (up to 25.93% for the FPGA and 70.22% for the ASIC) can be achieved by disabling the fault-tolerance at run-time.