Memory Sharing Approach for TMR Softcore Processor

Authors:
Yoshihiro Ichinomiya;Shiro Tanoue;Tomoyuki Ishida;Motoki Amagasaki;Morihiro Kuga;Toshinori Sueyoshi
Affiliations:
Graduate School of Science and Technology, Kumamoto University, Kumamoto, Japan 860-8555;Graduate School of Science and Technology, Kumamoto University, Kumamoto, Japan 860-8555;Graduate School of Science and Technology, Kumamoto University, Kumamoto, Japan 860-8555;Graduate School of Science and Technology, Kumamoto University, Kumamoto, Japan 860-8555;Graduate School of Science and Technology, Kumamoto University, Kumamoto, Japan 860-8555;Graduate School of Science and Technology, Kumamoto University, Kumamoto, Japan 860-8555
Venue:
ARC '09 Proceedings of the 5th International Workshop on Reconfigurable Computing: Architectures, Tools and Applications
Year:
2009

Citing 3
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Abstract

SRAM-based field programmable gate arrays (FPGAs) are more susceptible to single event upsets compared to ASIC . We focus on triple modular redundancy (TMR) to ensure high reliability. Herein, we study the implementation of TMR on a softcore processor called "Base TMR" for considering design flexibility, and evaluate the resource usage and operating frequency. To resolve these problems, we propose two types of TMR designs: "Memory Shared TMR" and "Cache Enabled TMR." Memory Shared TMR achieved efficient memory usage, but it reduced the operating frequency to about 25% in comparison with Base TMR. Cache Enabled TMR improved the operating frequency to a value similar to that of the base processor in exchange for 125% of memory usage overhead. Consequently, when implementing the TMR processor, we need to adopt an adequate TMR design by considering the trade-offs.