Fault-Tolerance Techniques for SRAM-Based FPGAs (Frontiers in Electronic Testing)

Evaluation of SEU and crosstalk effects in network-on-chip switches

SBCCI '06 Proceedings of the 19th annual symposium on Integrated circuits and systems design

Memory Sharing Approach for TMR Softcore Processor

ARC '09 Proceedings of the 5th International Workshop on Reconfigurable Computing: Architectures, Tools and Applications

SETmap: a soft error tolerant mapping algorithm for FPGA designs with low power

Proceedings of the 16th Asia and South Pacific Design Automation Conference

A framework for enabling fault tolerance in reconfigurable architectures

ARC'10 Proceedings of the 6th international conference on Reconfigurable Computing: architectures, Tools and Applications

Fast online error detection and correction with thread signature calculae

Microprocessors & Microsystems

Low-leakage soft error tolerant dual-port SRAM cells for cache memory applications

Microelectronics Journal

Fault recovery technique for TMR softcore processor system using partial reconfiguration

ICA3PP'12 Proceedings of the 12th international conference on Algorithms and Architectures for Parallel Processing - Volume Part I

GABES: A genetic algorithm based environment for SEU testing in SRAM-FPGAs

Journal of Systems Architecture: the EUROMICRO Journal

A low-cost fault tolerant solution targeting commercial FPGA devices

Journal of Systems Architecture: the EUROMICRO Journal

Design of the coarse-grained reconfigurable architecture DART with on-line error detection

Microprocessors & Microsystems